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sl811hs cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-08008 rev. *a revised march 14, 2002 sl811hs embedded usb host/slave controller
sl811hs document #: 38-08008 rev. *a page 2 of 29 table of contents 1.0 conventions .............................................................................................................. ................ 4 2.0 definitions .............................................................................................................. .................... 4 3.0 references ............................................................................................................... ................. 4 4.0 introduction ............................................................................................................. ................ 4 4.1 block diagram ............................................................................................................ .................... 4 4.2 sl811hs host or slave mode selection [master/slave mode] .................................................. 5 4.3 features ................................................................................................................. ......................... 5 4.4 data port, microprocessor interface ...................................................................................... ...... 6 4.5 interrupt controller ..................................................................................................... ................... 6 4.6 buffer memory ............................................................................................................ ................... 6 4.7 pll clock generator ...................................................................................................... ............... 6 4.8 usb transceiver .......................................................................................................... .................. 8 5.0 sl811hs registers ........................................................................................................ ........... 8 5.1 register values on power-up and reset .................................................................................... .9 5.2 usb control registers .................................................................................................... .............. 9 5.3 sl811hs control registers ................................................................................................ ........ 12 6.0 sl811hs and SL811HST-ac physical connections ...................................................... 16 6.1 sl811hs physical connections ............................................................................................. .... 16 6.2 SL811HST-ac physical connections ........................................................................................ 1 9 7.0 electrical specifications ................................................................................................ .22 7.1 absolute maximum ratings ................................................................................................. ....... 22 7.2 recommended operating condition ........................................................................................ 2 2 7.3 external clock input characteristics (x1) ................................................................................ .22 7.4 dc characteristics ....................................................................................................... ................ 23 7.5 usb host transceiver characteristics ..................................................................................... .23 7.6 bus interface timing requirements ........................................................................................ .. 24 8.0 package diagrams ....................................................................................................... ....... 28 list of figures figure 4-1. sl811hs usb host/slave controller functional block diagram ................................ 5 figure 4-2. full-speed 48-mhz crystal circuit ................................................................................ .. 7 figure 4-3. optional 12-mhz crystal circuit .................................................................................. .... 7 figure 6-1. sl811hs usb host/slave controller?pin layout ...................................................... 16 figure 6-2. SL811HST-ac usb host/slave controller pin layout ................................................ 19 list of tables table 6-1. sl811hs pin assignments and definitions ................................................................... 17 table 6-2. SL811HST-ac pin assignments and definitions ........................................................... 20
sl811hs document #: 38-08008 rev. *a page 3 of 29 license agreement use of this document and the intellectual properties contained herein indicates acceptance of the following license agreement. if you do not accept the terms of this license agreement, do not use this document, or the associated intellectual properties, or any other material you received in association with this product, and return this document and the associated materials within fifteen (15) days to cypress semiconductor corporation or (cy) or cy ? s authorized distributor from whom you purchased the product. 1. you can only legally obtain cy ? s intellectual properties contained in this document through cy or its authorized distributors. 2. you are granted a nontransferable license to use and to incorporate cy ? s intellectual properties contained in this document into your product. the product may be either for your own use or for sale. 3. you may not reverse-engineer the sl811hs or otherwise attempt to discover the designs of sl811hs. 4. you may not assign, distribute, sell, transfer or disclose cy ? s intellectual properties contained in this document to any other person or entity. 5. this license terminates if you fail to comply with any of the provisions of this agreement. you agree upon termination to des troy this document, stop using the intellectual properties contained in this document and any of its modification and incorporated or merged portions in any form, and destroy any unused sl811hs chips. warranty disclaimer and limited liability cypress (cy), hereafter referred to as the manufacturer, warrants that its products substantially conform to its specifications for a period of ninety (90) days from delivery as evidenced by the shipment records. the manufacturer's sole obligation and liabili ty for breaching the foregoing warranty shall be to replace or correct the defective products so that it substantially conforms to its specifications. any modification of the products by anyone other than the manufacturer voids the foregoing warranty. no other warranties are expressed and none shall be implied. the manufacturer makes no warrant for the use of its products. in order to minimize risks associated with customer ? s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. the manufacturer ? s products are not designed, authorized, or warranted suitable for use in life-support devices or systems or other critical applications. the manufacturer specifically excludes any implied warranties of merchantability and fitness for a particular purpose unless prohibited by law. in no event shall the manufacturer 's liability to you for damages hereunder for any cause whatsoever exceed the amount paid by you for the products. in no event will the manufacturer be liable for any loss of profits or other incidental or consequential damages arising out of the use or inability to use the product even if the manufacturer have been advised of the possibility of such damages. the manufacturer reserves the right to make changes at any time, without notice, to improve design or performance and supply the best product possible. the manufacturer assumes no responsibility for any errors that may appear in its technical document on the products nor does it make a commitment to update the information contained in its technical document. nothing contained in the technical documents of the products shall be construed as a recommendation to use any products in violation of existing patents, copyrights or other rights of third parties. no license is granted by implication or otherwise under any patent, paten t rights or other rights, of the manufacturer.
sl811hs document #: 38-08008 rev. *a page 4 of 29 1.0 conventions 1,2,3,4 numbers without annotations are decimals. dh, 1fh, 39h hexadecimal numbers are followed by an ? h. ? 0101b, 010101b binary numbers are followed by a ? b. ? brequest, n words in italics indicate terms defined by usb specification or by this specification. 2.0 definitions usb u niversal s erial b us sl811hs the sl811hs is a cypress usb host/slave controller, providing multiple functions on a single chip. this part is offered in both a 28-pin plcc package (sl811hs) and a 48-pin tqfp package (SL811HST-ac). throughout this document, ? sl811hs ? refers to both packages unless otherwise noted. note: this chip does not include cpu. sl11 the sl11 is a cypress usb peripheral device controller, providing multiple functions on a single chip. this part is offered in both a 28-pin plcc package (sl11) and a 48-pin tqfp package (sl11t-ac). throughout this document, ? sl11 ? refers to both packages unless otherwise noted. note: this chip does not include a cpu. sl11h the sl11h is a cypress usb host/slave controller, providing multiple functions on a single chip. this part is offered in both a 28-pin plcc package (sl11h) and a 48-pin tqfp package (sl11ht-ac). throughout this document, ? sl11h ? refers to both packages unless otherwise noted. note: this chip does not include cpu. lsb l east s ignificant b it msb m ost s ignificant b it r/w r ead/ w rite pll p hase l ock l oop ram r andom a ccess m emory sie s erial i nterface e ngine ack handshake packet indicates a positive acknowledgment. nak handshake packet indicating a negative acknowledgment usbd u niversal s erial b us d river sof s tart o f f rame is the first transaction in each frame. it allows endpoints to identify the start of the frame and synchronize internal endpoint clocks to the host. crc c yclic r edundancy c heck host the host computer system on which the usb host controller is installed 3.0 references [ref 1] usb specification 1.1: http://www.usb.org . 4.0 introduction 4.1 block diagram the sl811hs is an embedded usb host/slave controller capable of communicate with either full-speed or low-speed usb peripherals. the sl811hs can interface to devices such as microprocessors, microcontrollers, dsps, or directly to a variety of buses such as isa, pcmcia, and others. the sl811hs usb host controller conforms to usb specification 1.1. the sl811hs usb host/slave controller incorporates usb serial interface functionality along with internal full-/low-speed trans - ceivers. the sl811hs supports and operates in usb full-speed mode at 12 mbps, or at low-speed 1.5-mbps mode. the sl811hs data port and microprocessor interface provide an 8-bit data path i/o or dma bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as motorola or intel cpus and many others. inter- nally, the sl811hs contains a 256-byte ram data buffer which is used for control registers and data buffer. the available package types offered are a 28-pin plcc (sl811hs) and a 48-pin tqfp package (SL811HST-ac). both packages operate at 3.3 vdc. the i/o interface logic is 5v-tolerant.
sl811hs document #: 38-08008 rev. *a page 5 of 29 4.2 sl811hs host or slave mode selection [master/slave mode] sl811hs can work in two modes ? host or slave. for slave-mode operation and specification, please refer to the sl811s specification. this data sheet only covers host-mode operation. 4.3 features the only usb host/slave controller for embedded systems in the market with a standard microprocessor bus interface. supports both full-speed (12 mbps) and low-speed (1.5 mbps) usb transfer 4.3.1 usb specification compliance conforms to usb specification 1.1 4.3.2 cpu interface operates as a single usb host or slave under software control low-speed 1.5 mbps, and full speed 12 mbps, in both master and slave modes automatic detection of either low- or full-speed devices 8-bit bidirectional data, port i/o (dma supported in slave mode) on-chip sie and usb transceivers on-chip single root hub support 256-byte internal sram buffer, ping-pong operation operates from 12- or 48-mhz crystal or oscillator (built-in dpll) 5 v-tolerant interface suspend/resume, wake up, and low-power modes are supported auto-generation of sof and crc5/16 auto-address increment mode, saves memory read/write cycles development kit including source code drivers is available backward-compatible with sl11h, both pin and functionality 3.3v power source, 0.35 micron cmos technology available in both a 28-pin plcc package (sl811hs) and a 48-pin tqfp package (SL811HST-ac). x1 x2 d+ d- intr nwr nrd ncs nrst d0-7 generator usb root-hub xcvrs serial interface engine ram buffers control registers interrupt clock & controller processor interface master/slave controller figure 4-1. sl811hs usb host/slave controller functional block diagram
sl811hs document #: 38-08008 rev. *a page 6 of 29 4.4 data port, microprocessor interface the sl811hs microprocessor interface provides an 8-bit bidirectional data path along with appropriate control lines to interfac e to external processors or controllers. the control lines, chip select, read and write input strobes and a single address line, a0, along with the 8-bit data bus, support programmed i/o or memory mapped i/o designs. access to memory and control register space is a simple two step process, requiring an address write with a0 set = ? 0, ? followed by a register/memory read or write cycle with address line a0 set = ? 1. ? in addition, dma bidirectional interface in slave mode is available with handshake signals such as dreq, ack, wr, rd, cs and intr. please refer to the sl811s spec. the sl811hs write or read operation terminates when either nwr or ncs goes inactive. for devices interfacing to the sl811hs, that deactivate the chip select ncs before the write nwr, the data hold timing should be measured from the ncs and will be the same value as specified. thus, both intel ?? and motorola-type cpus can work easily with the sl811hs without any external glue logic requirements. 4.5 interrupt controller the sl811hs interrupt controller provides a single output signal (intrq) that can be activated by a number of events that may occur as result of usb activity. control and status registers are provided to allow the user to select single or multiple event s, which will generate an interrupt (assert intrq), and lets the user view interrupt status. the interrupts can be cleared by writ ing to the appropriate register (the status register at address 0x0d). 4.6 buffer memory the sl811hs contains 256 bytes of internal buffer memory. the first 16 bytes of memory represent control and status registers for programmed i/o operations. the remaining memory locations are used for data buffering (max. 240 bytes). access to the registers and data memory is through an external microprocessor, 8-bit data bus, in either of two addressing mode s, indexed or, if used with multiplexed address/data bus interfaces, direct access. with indexed addressing, the address is first written to the device with the a0 address line low, then the following cycle with a0 address line high is directed to the speci fied address. usb transactions are automatically routed to the memory buffer. control registers are provided, so that pointers and block sizes in buffer memory can be can set up. 4.6.1 auto address increment mode the sl811hs supports auto-increment mode for read or write cycles, a0 mode. in a0 mode, the micro controller sets up the address only once. on any subsequent data read or write access, the internal address pointer will advance to the next data location. 4.6.1.1 for example write 0x10 to sl811hs in address cycle (a0 is set low) write 0x55 to sl811hs in data cycle (a0 is set high) -> write 0x55 to location 0x10 write 0xaa to sl811hs in data cycle (a0 is set high) -> write 0xaa to location 0x11 write 0xbb to sl811hs in data cycle (a0 is set high) -> write 0xbb to location 0x12 the advantage of auto address increment mode is that it reduces the number of sl811hs memory read/write cycles required to move data to/from the device. for example, transferring 64-bytes of data to/from sl811hs using auto increment mode, will reduce the number of cycles to 1 address write and 64 read/write data cycles, compared to 64 address writes and 64 data cycles for random access. 4.7 pll clock generator either a 12-mhz or a 48-mhz external crystal can be used with the sl811hs. two pins, x1 and x2, are provided to connect a low-cost crystal circuit to the device as shown in figure 4-2 and figure 4-3 . if an external 48-mhz clock source is available in the application, it can be used instead of the crystal circuit by connecting the source directly to the x1 input pin. when a clock is used, the x2 pin is left unconnected.
sl811hs document #: 38-08008 rev. *a page 7 of 29 note: 1. cm (clock mode) pin of the sl811hs should be tied to gnd when 48-mhz xtal circuit or 48-mhz clock source is used. cbk 0.01 f rs 100 x1 48 mhz, series, 20-pf load cout 22 pf rf 1m x2 cin 22 pf lin 2.2 h x1 figure 4-2. full-speed 48-mhz crystal circuit x1 12 mhz , series, 20-pf load rf 1m cin 22 pf cout 22 pf rs 100 x2 x1 figure 4-3. optional 12-mhz crystal circuit
sl811hs document #: 38-08008 rev. *a page 8 of 29 4.7.1 typical crystal requirements the following are examples of ? typical requirements ? . please note that these specifications are generally found as standard crystal values and are therefore less expensive than custom values. if crystals are used in series circuits, load capacitance is not applicable. load capacitance of parallel circuits is a requirement. 4.8 usb transceiver the sl811hs has a built in transceiver that meets usb specification 1.1. the transceiver is capable of transmitting and receivi ng serial data at usb full speed (12 mbits) and low speed (1.5 mbits). the driver portion of the transceiver is differential while the receiver section is comprised of a differential receiver and two single-ended receivers. internally, the transceiver interfaces to the serial interface engine (sie) logic. externally, the transceiver connects to the physical layer of the usb. 5.0 sl811hs registers operation of the sl811hs is controlled through 16 internal registers. a portion of the internal ram is devoted to the control register space, and access is through the microprocessor interface. the registers provide control and status information for transactions on the usb, microprocessor interface, and interrupts. any write to control register 0fh will enable the sl811hs full features bit. this is an internal bit of the sl811hs that enable s additional features not supported by the sl11h. for sl11h hardware backward compatibility, this register should not be accessed. the table below shows the memory map and register mapping of both the sl11h and sl811hs. the sl11h is shown for users upgrading to the sl811hs. 12-mhz crystals: frequency tolerance: 100 ppm or better operating temperature range: 0 c to 70 c frequency: 12 mhz frequency drift over temperature: 50 ppm esr (series resistance): 60 ? load capacitance: 10 pf min. shunt capacitance: 7 pf max. drive level: 0.1 ? 0.5 mw operating mode: fundamental 48-mhz crystals: frequency tolerance: 100 ppm or better operating temperature range: 0 c to 70 c frequency: 48 mhz frequency drift over temperature: 50 ppm esr (series resistance): 40 ? load capacitance: 10 pf min. shunt capacitance: 7 pf max. drive level: 0.1 ? 0.5 mw operating mode: third overtone
sl811hs document #: 38-08008 rev. *a page 9 of 29 the registers in the sl811hs are divided into two major groups. the first group is referred to as usb control registers. these registers enable and provide status for control of usb transactions and data flow. the second group of registers provides contr ol and status for all other operations. 5.1 register values on power-up and reset the following registers initialize to zero on power-up and reset: usb-a/usb-b host control register [00h, 08h] bit 0 only control register 1 [05h] usb address register [07h] current data set/hardware revision/sof counter low register [0eh] all other registers power-up and reset in an unknown state and should be initialized by firmware. 5.2 usb control registers communication and data flow on the usb uses the sl811hs ? s usb a-b control registers. the sl811hs can communicate with any usb device functions and any specific endpoints via the usba or usbb register sets. the usb a-b host control registers can be used in a ping-pong arrangement to manage traffic on the usb. the usb host control register also provides a means to interrupt an external cpu or micro controller when one of the usb protocol transac- tions is completed. the table above shows the two sets of usb host control registers, the ? a ? set and ? b ? set. the two register sets allow for overlapped operation. when one set of parameters is being set up, the other is transferring. on completion of a transfer to an endpoint, the next operation will be controlled by the other register set. note . on the sl11h, the usb-b set control registers are not used. the usb-b register set can be used only when sl811hs mode is enabled by initializing register 0fh. the sl811hs usb host control has two groups of five registers each, which map in the sl811hs memory space. these registers are defined in the following tables. register name sl11h and sl811hs sl11h (hex) address sl811hs (hex) address usb-a host control register 00h 00h usb-a host base address 01h 01h usb-a host base length 02h 02h usb-a host pid, device endpoint (write)/usb status (read) 03h 03h usb-a host device address (write)/transfer count (read) 04h 04h control register1 05h 05h interrupt enable register 06h 06 h reserved register reserved reserved usb-b host control register reserved 08h usb-b host base address reserved 09h usb-b host base length reserved 0ah usb-b host pid, device endpoint (write)/usb status (read) reserved 0bh usb-b host device address (write)/transfer count (read) reserved 0ch status register 0dh 0dh sof counter low (write)/hw revision register (read) 0eh 0e h sof counter high and control register2 reserved 0f h memory buffer 10h-ffh 10h-ffh
sl811hs document #: 38-08008 rev. *a page 10 of 29 bit 3 is reserved for future usage. the sl811hs uses bit 5 to enable transfer of a data packet after a sof packet is transmitted. when this bit set ? 1, ? the next enabled packet will be sent after next sof. if set = ? 0 ? the next packet is sent immediately if the sie is free. the sl811hs automatically generates preamble packets when bit 7 is set. this bit is only used to send packets to a low-speed device through a hub. to communicate to a full speed device, this bit is set to zero. for example, when sl811hs communicates to a low-speed device via the hub: ? sl811hs sie should set to operate at 48 mhz, i.e., bit 5 of register 05h should be set = ? 0. ? ? bit 6 of register 0fh should be set = ? 0, ? set correct polarity of data+ and data ? state for full speed. ? bit 7, preamble bit, should be set = ? 1 ? in host control register. when sl811hs communicates directly to low-speed device: ? sl811hs. bit 5 of register 05h should be set = ? 1. ? ? bit 6 of register 0fh should be set = ? 1, ? data+ and data ? polarity for low speed. ? the state of bit 7 is ignored in this mode. 5.2.3 example of sl811hs usb packet transfer sl811hs memory set-up as shown: 03h-04h register will contain pid and device endpoint and device address. 10h-ffh usb data as required. 5.2.1 sl811hs host control registers register name sl11h and sl811h sl11h (hex) address sl811hs (hex) address usb-a host control register 00h 00h usb-a host base address 01h 01h usb-a host base length 02h 02h usb-a host pid, device endpoint (write)/usb status (read) 03h 03h usb-a host device address (write)/transfer count (read) 04h 04h usb-b host control register reserved 08h usb-b host base address reserved 09h usb-b host base length reserved 0ah usb-b host pid, device endpoint (write)/usb status (read) reserved 0bh usb-b host device address (write)/transfer count (read) reserved 0ch 5.2.2 usb-a/usb-b host control registers [00h, 08h] bit position bit name function 0 arm allows enabled transfers when set = ? 1. ? cleared to ? 0 ? when transfer is complete. 1 enable when set = ? 1 ? allows transfers to this endpoint. when set ? 0 ? usb transactions are ignored. if enable = ? 1 ? and arm = '0' the endpoint will return naks to usb transmissions. 2 direction when set = ? 1 ? transmit to host. when ? 0 ? receive from host. 3 reserved 4 iso when set to ? 1 ? allows isochronous mode for this endpoint. 5 sof ? 1 ? = synchronize with the sof transfer 6 data toggle bit ? 0 ? if data0, ? 1 ? if data1. 7 preamble if set = ? 1 ? a preamble token is transmitted prior to transfer of low-speed packet. if set = ? 0, ? preamble generation is disabled.
sl811hs document #: 38-08008 rev. *a page 11 of 29 5.2.4 sof packet generation the sl811hs automatically computes crc5 by hardware. no crc or sof is required to be generated by external firmware for sl811hs. 5.2.5 usb-a/usb-b host base address [01h, 09h] the usb-a/usb-b base address is a pointer to the sl811hs memory buffer location for usb reads and writes. when trans- ferring data out (host to device), the usb-a and usb-b can be set up prior to setting arm on the usb-a or usb-b host control register. see the software implementation example. 5.2.6 usb-a/usb-b host base length [02h, 0ah] the usb a/b host base register contains the maximum packet size to be transferred between the sl811hs and a slave usb peripheral. essentially, this designates the largest packet size that can be transferred by the sl811hs. base length designates the size of data packet to be sent. for example, in bulk mode the maximum packet length is 64 bytes. in iso mode, the maximum packet length is 1023, since the sl811hs only has an 8-bit length; the maximum packet size for the iso mode using the sl811hs is 255 ? 16 bytes. when the host base length register is set to zero, a zero-length packet will be transferred. 5.2.7 usb-a/usb-b host pid, device endpoint (write)/usb status (read) [03h, 0bh] this register has two modes. when read, this register provides packet status and it contains information relative to the last packet that has been received or transmitted. the register is defined as follows. when written, this register provides the pid and endpoint information to the usb sie engine to be used in the next transaction. all sixteen endpoints can be addressed by the sl811hs. pid3-0 4-bit pid field (see table below) ep3-0 4-bit endpoint value in binary. bit position bit name function 0 ack transmission acknowledge 1 error error detected in transmission 2 time-out time-out occurred 3 sequence sequence bit. ? 0 ? if data0, ? 1 ? if data1 4 setup ? 1 ? indicates setup packet 5 overflow overflow condition - maximum length exceeded during receives 6 nak slave returns nak 7 stall slave set stall bit d7 d6 d5 d4 d3 d2 d1 d0 pid3 pid2 pid1 pid0 ep3 ep2 ep1 ep0 pid type d7-d4 setup 1101 (d hex) in 1001 (9 hex) out 0001 (1 hex) sof 0101 (5 hex) preamble 1100 (c hex) nak 1010 (a hex) stall 1110 (e hex) data0 0011 (3 hex) data1 1011 (b hex)
sl811hs document #: 38-08008 rev. *a page 12 of 29 5.2.8 usb-a/usb-b host transfer count register (read), usb address (write) [04h, 0ch] this register has two functions. when read, this register contains the number of bytes left over (from ? length ? field) after a packet is transferred. if an overflow condition occurs, i.e., the received packet from slave usb device was greater than the length fi eld specified, a bit is set in the packet status register indicating the condition. when written, this register will contain the us b device address to which the host wishes to communicate. da6-da0 device address, up to 127 devices can be addressed da7 reserved bit should be set zero. 5.3 sl811hs control registers 5.3.1 control register 1, address [05h] the control register 05h enables/disables usb transfer operation with control bits defined as follows. at power-up this register will be cleared to all zeros. in the sl811hs, bit 0 is used to enable hw sof auto-generation (bit 0 was not used in the sl11h). d7 d6 d5 d4 d3 d2 d1 d0 0 da6 da5 da4 da3 da2 da1 da0 register name sl11h and sl811h sl11h (hex) address sl811hs (hex) address control register1 05h 05h interrupt enable register 06h 06 h reserved register 07h 07 h status register 0dh 0dh sof counter low (write)/hw revision register (read) 0eh 0e h sof counter high and control register2 reserved 0f h memory buffer 10h-ffh 10h-ffh bit bit name function 0 sof ena/dis ? 1 ? enable auto hardware sof generation, ? 0 ? = disable 1 reserved 2 reserved 3 usb engine reset usb engine reset = ? 1. ? normal set ? 0 ? 4 j-k state force see the table below 5 usb speed ? 0 ? set-up for full speed, ? 1 ? set-up low-speed 6 suspend ? 1 ? enable, ? 0 ? = disable 7 reserved
sl811hs document #: 38-08008 rev. *a page 13 of 29 5.3.2 j-k programming states [bits 3 and 4 of control register 05h] the j-k force state control and usb engine reset bits can be used to generate usb reset condition on the usb. forcing k-state can be used for peripheral device remote wake-up, resume and other modes. these two bits are set to zero on power-up. 5.3.3 low-speed/full speed modes [bit 5 control register 05h] the sl811hs is designed to communicate with either full or low-speed devices. at power-up bit 5 will be set low, i.e., for full speed. there are two cases when communicating with a low-speed device. when a low-speed device is connected directly to the sl811hs, bit 5 of register 05h should be set to logic ? 1 ? and bit 6 of register 0fh, output-invert, needs to be set to ? 1 ? in order to change the polarity of d+ and d ? . when a low-speed device is connected via a hub to sl811hs, bit 5 of register 05h should be set to logic ? 0 ? and bit 6 of register 0fh should be set to logic ? 0 ? in order to keep the polarity of d+ and d ? for full speed. in addition, make sure that bit 7 of usb-a/usb-b host control registers [00h, 08h] is set to ? 1. ? 5.3.4 low-power modes [bit 6 control register 05h] when bit-6 (suspend) is set to ? 1, ? the power of the transmit transceiver will be turned off, the internal ram will be in the suspend mode, and the internal clocks will be disabled. note . any activity on the usb bus (i.e., k-state, etc.) will resume normal operation. to resume normal operation from the cpu side, a data write cycle (i.e., a0 set high for a data write cycle) should be done. 5.3.5 interrupt enable register, address [06h] the sl811hs provides an interrupt request output, which can be activated on a number of conditions. the interrupt enable register allows the user to select conditions that will result in an interrupt being issued to an external cpu. a separate inte rrupt status register is provided. it can be polled in order to determine those conditions that initiated the interrupt. (see interru pt status register description.) when a bit is set to ? 1 ? the corresponding interrupt is enabled. bits 0 ? 1 are used for the usb a/b controller interrupt. bit 4 is used to enable/disable the sof timer. to utilize this bit function, bit 0 of register 05h must be enabled and the sof counter registers 0eh and 0fh must be initialized. bit 5 is used to enable/disable the device inserted/removed interrupt. when bit-6 of register 05h is set = ? 1, ? bit 6 of this register enables the resume detect interrupt. otherwise, this bit is used to enable device detection status as defined in the interrupt status register bit definitions. note: 2. force k-state for low speed. 3. force j-state for low speed. bit 4 bit 3 function 0 0 normal operating mode 0 1 force usb reset, d+ and d ? are set low (se0) 1 0 force j-state, d+ set high, d ? set low [2] 1 1 force k-state, d ? set high, d+ set low [3] bit position bit name function 0 usb-a usb-a done interrupt 1 usb-b usb-b done interrupt 2 reserved 3 reserved 4 sof timer 1 = enable interrupt on 1-ms sof timer 5 inserted/removed slave insert/remove detection 6 device detect/resume enable device detect/resume interrupt
sl811hs document #: 38-08008 rev. *a page 14 of 29 5.3.6 usb address register, reserved, address [07h] this register is reserved for the device usb address in slave operation. it should not be written by the user. 5.3.7 interrupt status register, address [0dh] the isr is a read/write register providing interrupt status. interrupts can be cleared by writing to this register. to clear a specific interrupt, the register is written with corresponding bit set to ? 1. ? bit 5 is provided to support usb cable insertion/removal for the sl811hs in host mode. this bit is set when a transition from se0 to idle (device inserted) or idle to se0 (device removed) occurs on the bus. bit 6 is shared between device detection status and resume detection interrupt. when bit-6 of register 05h is set to one, this bit will be the resume detection interrupt bit. otherwise, this bit is used to indicate the presence of a device, ? 1 ? = device ? not present ? and ? 0 ? = device ? present. ? in this mode this bit should be checked along with bit 5 to determine whether a device has been inserted or removed. bit 7 provides continuous usb data+ line status. once it has been determined that a device has been inserted as described above with bits 5 and 6, bit 7 can be used to detect if the inserted device is low- or full-speed. 5.3.8 current data set register/hardware revision/sof counter low, address [0eh] this register has two modes: a read from this register indicates the current sl811hs silicon revision. writing to this register will set up auto generation of sof to all connected peripherals. this counter is based on the 12-mhz clock. to set up a 1-ms timer interval, the software must set up both sof counter registers to the proper values. example . to set up sof for 1-ms interval, sof counter register 0eh should be set to e0h. bit position bit name function 0 usb-a usb-a done interrupt 1 usb-b usb-b done interrupt 2 reserved 3 reserved 4 sof timer 1 = interrupt on 1-ms sof timer 5 insert/remove slave insert/remove detection 6 device detect/resume device detect/resume interrupt 7 d+ value of the data+ pin bit position bit name function 0 reserved reserved for slave 1 reserved reserved for slave 2 reserved read will be zero 3 reserved read will be zero 4 ? 7 hw revision sl11h read = 0h, sl811hs rev1.2 read = 1h, sl811hs rev1.5 read = 2 bit position bit name function 0 ? 7 sof low counter register write-only to set sof low counter register, oeh
sl811hs document #: 38-08008 rev. *a page 15 of 29 5.3.9 sof counter high/control2 register, address [0fh, read/write] when writing to this register the bits definition are defined as follows. note . any write to control register 0fh will enable the sl811hs full features bit. this is an internal bit of the sl811hs which enables additional features not supported by the sl11h. for sl11h hardware backward compatibility, this register should not be accessed. the usb-b register set can be used when sl811hs full feature bit is enabled. example . to set up for 1-ms sof time: the register 0fh contains the upper 6 bits of the sof timer. register 0eh contains the lower 8 bits of the sof timer. the timer is based on a 12-mhz clock and uses a counter, which counts down to zero from an initial value. to set the timer for 1 ms time, the register 0eh should be loaded with value e0h, register 0f, bits 0 ? 5 should be loaded with 2eh. to start the timer, bit 0 of register 05h should be set to ? 1. ? to load both high and low registers with the proper values the user must follow this sequence: ? write e0h to register 0eh. ? write 2eh to register 0fh, bits 0 ? 5. bits 6 and 7 should be set for appropriate function: polarity and master/slave. ? enable bit 0 in register 05h. note . any write to the 0fh register will clear the internal frame counter. register 0fh must be written at least once after power-u p. the internal frame counter is incremented after every sof timer tick. the internal frame counter is an 11-bit counter, which is used to track the frame number. the frame number is incremented after each timer tick. its contents are transmitted to the slav e every millisecond in a sof packet. c13 ? c6 top 8 bits of 14-bit sof counter. when read, this register will return the value of the sof counter divided by 64. the software should use this register to deter mine the available bandwidth in the current frame before initiating any usb transfer. in this way, the user will be able to avoid ba bble conditions on the usb. for example, to determine the available bandwidth left in a frame: maximum number of clock ticks in 1-ms time frame is 12000(1 count per 12-mhz clock period, or approximately 84 ns.) the value read back in register 0fh is the (count 64) 84 ns = time remaining in current frame. usb bit time = one 12-mhz period. value of register 0fh available bit times left are between bbh 12000 bits to 11968 (187 64) bits bah 11968 bits to 11904 (186 64) bits bit position bit name function 0 ? 5 sof high counter register write a value or read it back to sof high counter register 6 sl811hs d+/d ? data polarity swap write/read, set ? 1 ? change polarity, ? 0 ? no change of polarity 7 sl811hs master/slave selection write/read, ? 1 ? is master, else slave d7 d6 d5 d4 d3 d2 d1 d0 c13 c12 c11 c10 c9 c8 c7 c6
sl811hs document #: 38-08008 rev. *a page 16 of 29 6.0 sl811hs and SL811HST-ac physical connections this part is offered in both a 28-pin plcc package (sl811hs) and a 48-pin tqfp package (SL811HST-ac). 6.1 sl811hs physical connections 6.1.1 sl811hs pin layout pins 2 and 3 should be no connect in host mode. see pin and signal description. 6.1.2 28-pin plcc mechanical dimensions 1 228 nc* nc* nrd nwr d7 d6 d5 d4 gnd d3 d2 d1 d0 gnd intrq vdd1 nrst vdd2 gnd ncs data- data+ vdd1 clk/x1 x2 sl811hsh 28 plcc a0 m/s 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 24 22 21 20 19 18 27 26 23 cm figure 6-1. sl811hs usb host/slave controller ? pin layout
sl811hs document #: 38-08008 rev. *a page 17 of 29 6.1.3 sl811hs usb host controller pins description the sl811hs package is a 28-pin plcc. the device requires 3.3 vdc. average typical current consumption is less then 20 ma for 3.3v. notes: 4. the a0 address bit is used to access address or data registers in i/o-mapped or memory-mapped applications. 5. the cm clock multiplier pin should be tied high for a 12-mhz clock source and tied to ground for a 48-mhz clock source. in sl 11h, this pin was designated as an ale input pin. 6. v dd can be derived from the usb supply. the diagram below shows a simple method to provide 3.3v/30 ma. another option is to use a torex semiconductor, ltd. 3.3v smd regulator (part number xc62hr3302mr). 7. the x1/x2 clock requires external 12- or 48-mhz matching crystal or clock source. table 6-1. sl811hs pin assignments and definitions pin no. pin type pin name pin description 1 in a0 a0 = ? 0. ? selects address pointer . reg. write only. selects data buffer or register. r/w. [4] 2 in ndack dma acknowledge . an active low input used to interface to an external dma controller. this works only in slave mode. in host mode, pin should be tied to logic ? 1 ? in host mode. 3 out ndrq dma request . an active low output used with an external dma controller. ndrq and ndack form the handshake for dma data transfers. in host mode, pin must be left unconnected in host mode. 4 in nrd read strobe input . an active low input used with ncs to read registers/data memory. 5 in nwr write strobe input . an active low input used with ncs to write to registers/data memory. 6 in ncs active low chip select . used with nrd and nwd when accessing sl811hs. 7 in cm clock mode . select internal 4 x clock multiplier. ? 1 ? enables 4x clock multiplier. ? 0 ? disables. [5] 8 vdd1 +3.3 vdc power for usb transceivers 9 bidir data + usb differential data signal high side 10 bidir data - usb differential data signal low side 11 gnd usb gnd ground connection for usb 12 vdd +3.3 vdc sl811hs device v dd power [6] 13 in clk/x1 12-/48-mhz clock or external crystal x1 connection [7] 14 out x2 external crystal x2 connection 15 in nrst sl811hs device active low reset input 16 out intrq active high interrupt request output to external controller 17 gnd gnd sl811hs device ground 18 bidir d0 data 0. microprocessor data/(address) bus 19 bidir d1 data 1. microprocessor data/(address) bus 20 bidir d2 data 2. microprocessor data/(address) bus 21 bidir d3 data 3. microprocessor data/(address) bus 22 gnd gnd sl811hs device ground 23 bidir d4 data 4. microprocessor data/(address) bus 24 bidir d5 data 5. microprocessor data/(address) bus 25 bidir d6 data 6. microprocessor data/(address) bus 26 bidir d7 data 7. microprocessor data/(address) bus 27 in m/s master/slave select. host = ? 0, ? slave = ? 1 ? 28 vdd +3.3 vdc sl811hs device v dd power
sl811hs document #: 38-08008 rev. *a page 18 of 29 the diagram below illustrates a simple +3.3v voltage source. 6.1.4 package markings (sl811hs) yyww = date code xxxx = product code x.x = silicon revision number 9 86% *1' 5

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sl811hs document #: 38-08008 rev. *a page 19 of 29 6.2 SL811HST-ac physical connections 6.2.1 SL811HST-ac pin layout 6.2.2 mechanical dimensions 48-pin tqfp note: 8. nc. indicates no connection. nc pins should be left unconnected. SL811HST 1 12 13 24 25 48 37 36 nc nc nc nc nc nc nc nc nc nc data- nrd nc nc nc nc nc nwr ncs cm vdd1 data+ vdd clk/x1 x2 nrst intrq gnd d0 d1 d2 d3 gnd d4 d5 d6 d7 vdd m/sdd a0 nc nc [16] nc usbgnd nc nc nc nc figure 6-2. SL811HST-ac usb host/slave controller pin layout
sl811hs document #: 38-08008 rev. *a page 20 of 29 6.2.3 SL811HST-ac usb host controller pins description the SL811HST-ac is packaged in a 48-pin tqfp. the device requires a 3.3vdc power source. the SL811HST-ac requires an external 12 or 48 mhz crystal or clock. table 6-2. SL811HST-ac pin assignments and definitions pin no. pin type pin name pin description 1 nc nc nc 2 nc nc nc 3 in nwr write strobe input . an active low input used with ncs to write to registers/data memory. 4 in ncs active low SL811HST-ac chip select . used with nrd and nwr when accessing sl811ht. 5 in cm clock mode . select 12-mhz/48-mhz clock source. [9] 6 vdd1 +3.3 vdc power for usb transceivers . v dd1 may be connected to v dd . 7 bidir data + usb differential data signal high side 8 bidir data - usb differential data signal low side 9 gnd usb gnd ground connection for usb 10 nc nc nc 11 nc nc nc 12 nc nc nc 13 nc nc nc 14 nc nc nc 15 vdd +3.3 vdc SL811HST-ac device v dd power [10] 16 in clk/x1 clock or external crystal x1 connection [11] 17 out x2 external crystal x2 connection 18 in nrst SL811HST-ac device active low reset input 19 out intrq active high interrupt request output to external controller 20 gnd gnd SL811HST-ac device ground 21 bidir d0 data 0 . microprocessor data/(address) bus. 22 nc nc nc 23 nc nc nc 24 nc nc nc 25 nc nc nc 26 nc nc nc 27 bidir d1 data 1 . microprocessor data/(address) bus. 28 bidir d2 data 2 . microprocessor data/(address) bus. 29 bidir d3 data 3 . microprocessor data/(address) bus. 30 gnd gnd SL811HST-ac device ground 31 bidir d4 data 4 . microprocessor data/(address) bus. 32 bidir d5 data 5 . microprocessor data/(address) bus. notes: 9. the cm clock multiplier pin should be tied high for a 12-mhz clock source and tied to ground for a 48-mhz clock source. in sl 11h, this pin was designated as ale input pin. 10. vdd can be derived from the usb supply. see diagram. 11. the x1/x2 clock requires external 12- or 48-mhz matching crystal or clock source.
sl811hs document #: 38-08008 rev. *a page 21 of 29 notes: 12. the a0 address bit is used to access address register or data registers in i/o mapped or memory mapped applications. 6.2.4 package markings (SL811HST-ac) yyww = date code xxxx = product code x.x = silicon revision number 33 bidir d6 data 6 . microprocessor data/(address) bus. 34 nc nc nc 35 nc nc nc 36 nc nc nc 37 nc nc nc 38 nc nc nc 39 bidir d7 data 7 . microprocessor data/(address) bus. 40 in m/s master/slave mode select . ? 1 ? selects slave. ? 0 ? = master. 41 vdd +3.3 vdc SL811HST-ac device v dd power. 42 in a0 a0 = ? 0. ? selects address pointer. reg.a0 = ? 1. ? selects data buffer or register. [12] 43 in ndack dma acknowledge . an active low input used to interface to an external dma controller. dma is enabled only in slave mode. in host mode, pin should be tied high (logic ? 1 ? ) . 44 out ndrq dma request . an active low output used with an external dma controller. ndrq and ndack form the handshake for dma data transfers. in host mode, pin must be left unconnected . 45 in nrd read strobe input . an active low input used with ncs to read registers/data memory. 46 nc nc nc 47 nc nc nc 48 nc nc nc table 6-2. SL811HST-ac pin assignments and definitions (continued) pin no. pin type pin name pin description SL811HST yyww-x.x xxxx
sl811hs document #: 38-08008 rev. *a page 22 of 29 7.0 electrical specifications 7.1 absolute maximum ratings this section lists the absolute maximum ratings of the sl811hs. stresses above those listed can cause permanent damage to the device. exposure to maximum rated conditions for extended periods can affect device operation and reliability. 7.2 recommended operating condition 7.3 external clock input characteristics (x1) notes: 13. the sl811hs can use a 12-mhz crystal oscillator or 12-mhz clock source. 14. fundamental mode for 12-mhz crystal. 15. the sl811hs can use a 12-mhz clock source. storage temperature ? 40 c to 125 c voltage on any pin with respect to ground ? 0.3v to 6.0v power supply voltage (v dd ) 4.0 v power supply voltage (v dd1 ) 4.0 v lead temperature (10 seconds) 180 c parameter min. typical max. power supply voltage, vdd 3.0v 3.3 v 3.45v power supply voltage, vdd1 3.0v 3.45v operating temperature 0 c 65 c crystal requirements, (x1, x2) min. typical max. operating temperature range 0 c 65 c parallel resonant frequency [13] 48 mhz frequency drift over temperature 50 ppm accuracy of adjustment 30 ppm series resistance 100 ohms shunt capacitance 3 pf 6 pf load capacitance 20 pf drive level 20 w 5 mw mode of vibration third overtone [14] parameter min. typical max. clock input voltage @ x1 (x2 open) 1.5 v clock frequency [15] 48 mhz
sl811hs document #: 38-08008 rev. *a page 23 of 29 7.4 dc characteristics 7.5 usb host transceiver characteristics every v dd pin, including usb v dd , has to have a decoupling capacitor to ensure clean v dd (free of high-frequency noise) at the chip input point (pin) itself. the best way to do this is to connect a ceramic capacitor (0.1 f, 6v) between the pin itself and a good ground. capacitor leads must be kept as short as possible. use surface mount capacitors with the shortest traces possible (the use of a ground plane is strongly recommended). parameter description min. typ. max. v il input voltage low ? 0.3 v 0.8v v ih input voltage high (5v tolerant i/o) 2.0 v 6.0v v ol output voltage low (i ol = 4 ma) 0.4v v oh output voltage high (i oh = ? 4 ma) 2.4 v i oh output current high 4 ma i ol output current low 4 ma i ll input leakage 1 a c in input capacitance 10 pf i cc [16] supply current (v dd ) inc usb @fs 21 ma 25 ma i ccsus1 [17] supply current (v dd ) suspend w/clk & pll enb 4.2 ma 5 ma i ccsus2 [18] supply current (v dd ) suspend no clk & pll dis 50 a 60 a i usb supply current (v dd1 ) 10 ma i usbsus transceiver supply current in suspend 10 a parameter description min. typ. [19] max. v ihys differential input sensitivity (data+, data ? ) 0.2v 200 mv v usbih usb input voltage high driven 2.0 v usbil usb input voltage low 0.8v v usboh usb output voltage high 2.0v v usbol usb output voltage low 0.0v 0.3 v z usbh [20] output impedance high state 36 ohms 42 ohms z usbl [20] output impedance low state 36 ohms 42 ohms i usb transceiver supply p-p current (3.3v) 10 ma @ fs notes: 16. i cc measurement includes usb transceiver current (i usb ) operating at full speed. 17. i ccsus1 measured with 12-mhz clock input and internal pll enabled. suspend set ? (usb transceiver and internal clocking disabled). 18. i ccsus2 measured with external clock, pll disabled, and suspend set. for absolute minimum current consumption, ensure that all inputs to the device are at static logic level. 19. all typical values are v dd = 3.3v and t amb = 25 c. 20. = 86%; impedance values includes an external resistor of 24 ohms 1% (sl811hs revision 1.2 requires external resistor values of 33 o hms 1%).
sl811hs document #: 38-08008 rev. *a page 24 of 29 7.6 bus interface timing requirements 7.6.1 i/o write cycle note: ncs an be held low for multiple write cycles provided nwr is cycled. write cycle time for auto inc mode writes is 150 ns minimum. parameter description min. typ. max. t wr write pulse width 65 ns t wcsu chip select set-up to nwr low 0 ns t wshld chip select hold time after nwr high 0 ns t wasu a0 address set-up time 65 ns t wahld a0 address hold time 10 ns t wdsu data to write high set-up time 60 ns t wdhld data hold time after write high 5 ns t cscs ncs inactive to ncs* asserted 85 ns t wrhigh nwr high 85 ns nwr a0 d0-d7 data twr twahld twdhld twasu twdsu twdsu twdhld i/o write cycle to register or memory buffer register or memory address ncs twcsu twshld tcscs see note. twrhigh
sl811hs document #: 38-08008 rev. *a page 25 of 29 7.6.2 i/o read cycle note . ncs can be kept low during multiple read cycles provided nrd is cycled. rd cycle time for auto inc mode reads is 150 ns minimum. parameter description min. typ. max. t wr write pulse width 65 ns t rd read pulse width 65 ns t wcsu chip select set-up to nwr 0 ns t wasu a0 address set-up time 65 ns t wahld a0 address hold time 10 ns t wdsu data to write high set-up time 60 ns t wdhld data hold time after write high 5 ns t racc data valid after read low 20 ns 25 ns t rdhld data hold after read high 5 ns t rcsu chip select low to read low 0 ns t rshld ncs hold after read high 0 ns t cscs * ncs inactive to ncs *asserted 85 ns t wrrdl nwr high to nrd low 85ns nrd a0 d0-d7 data twr twahld twdhld twasu twdsu trdhld i/o read cycle from register or memory buffer register or memory address trdp nwr trshld trcsu ncs tracc tcscs *note twrrdl
sl811hs document #: 38-08008 rev. *a page 26 of 29 7.6.3 reset timing note . clock is 48-mhz nominal. parameter description min. typ. max. t reset nrst pulse width 16 clocks t ioact nrst high to nrd or nwr active 16 clocks nrst nrd or nwr treset tioact reset timing
sl811hs document #: 38-08008 rev. *a page 27 of 29 7.6.4 clock timing specifications parameter description min. typ. max. t clk clock period (48 mhz) 20.0 ns 20.8 ns t high clock high time 9 ns 11 ns t low clock low time 9 ns 11 ns t rise clock rise time 5.0 ns t fall clock fall time 5.0 ns clock duty cycle 45% 55% clk clock timing trise tfall thigh tclk tlow
sl811hs document #: 38-08008 rev. *a page 28 of 29 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. 8.0 package diagrams intel is a registered trademark of intel corporation. torex is a trademark of torex semiconductors, ltd. sl811hs is a trademark of cypress semiconductor corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. 28-pin plcc 48-pin tqfp
sl811hs document #: 38-08008 rev. *a page 29 of 29 document title: sl811hs usb host/slave controllers hardware specification document number: 38-08008 rev. ecn no. issue date orig. of change description of change ** 110850 12/14/01 bha converted to cypress format from scanlogic *a 112687 03/22/02 mul 1) changed power supply voltage to 4.0v in section 7.1 2) changed value of twdsu in section 7.6.2 3) changed max. power supply voltage to 3.45 v in section 7.2 4) changed accuracy of adjustment in section 7.2 5) changed bits 0 and 1 to reserved in section 5.3.8 6) changed bit 2 to reserved in section 5.3.5 and 5.3.7 7) changed bit 2 to reserved in section 5.3.1 8) changed definition of bit 6 in section 5.3.5 & 5.3.7 9) added section 5.1, register values on power-up and reset 10) changed bit description notes in section 5.3.7 11) changed note about series termination resistors in section 7.5 12) changed example in section 5.3.9 13) changed j-k programming states table in section 5.3.2 14) added and removed comments for low-power modes in section 5.3.4 15) removed sections specific to slave operation and sl11h 16) removed duplicate tables 17) general formatting changes to section headings 18) fixed all part number references 19) added comments to section 7.5 and new definitions to section 2.0

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